41J Blog

I bought some OP177G in SOIC8 on eBay. The strange thing about them was that while I bought 10 on the same piece of cut tape, the packages were different… I figured there was a high probability that they were fake.

I decapped them using an Olfa cutter (box cutter) blade. All things considered this decapping process works surprisingly well. With some effort, I think you can do better (@marcan42 has used this method with reasonable results which is what gave me the idea in the first place).

They were imaged under the same inspection microscope (Amscope) that I use for soldering. While the images are not great, the feature sizes are huge so it doesn’t matter so much.

I also purchased some OP177s from Digikey… turns out that while the packages look kind of fake, the dies appear to be identical!

More pictures follow:

The Keithley 2002 is an 8.5 digit multimeter. This puts it among the highest precision multimeters available. I’ve been curious about the ADCs used in these high end multimeters and have been looking over the Keithley 2002 ADC schematic. These are my notes.

The schematic I used is from TiN. Originally this was hosted here but appears to currently be offline. A local copy of the schematic is here.

As far as I can understand the ADC is a dual slope implementation (UPDATE: it’s actually multislope, but the slow slope is always connected, see below). The slopes are driven by current sources of ~450uA (which are derived from a 7V reference). They are switched through a SD5400, and when not in use flow to some kind of current sink.

I’ve mostly looked at the current sources, and switching. As part of this, I’ve been playing with an LTSPICE simulation (download):

The Keithley 2002 uses a 7V LTZ1000 reference (generally regarded as the best voltage reference you can buy). This enters the ADC board as a differential signal (REFHI and REFLO). REFHI should be 7V and REFLO ~GND. The REFHI is used to feed a non-inverting opamp (U801). The opamp has gain of 1.666. A tap is taken off the feedback network of U801 at ~2.333V. This is used as the reference for U816. This opamp drives a JFET (Q805) such that 2.333V flows through it. Creating a current source. Setting the voltage through Q805 seems to set the current at ~-450uA.

Rather than being ground referenced, the feedback network of U801 is connected to the virtual ground of U802. U802 is referenced to REFLO. U802 is an inverting opamp. Again with a gain of 1.666. Again a tap is taken off the feedback network at ~-2.333V. This is used as the reference for a opamp driving a current source created by Q806 (similar to the above). Current though Q806 is ~450uA.

The above therefore creates positive and negative current sources of +/- 450uA. These are the run down slopes of this dual slope implementation.

There’s another current source, Q807. This goes directly to the integrator. I don’t understand it’s purpose…

UPDATE: Kleinstein on the EEVBlog forums pointed out that there is a single slower slope which is always connected, delivering ~5uA. I assume this is what U815/Q807 are. So this is in fact a multislope ADC, but the slow slope is always connected.

The references are switched through an SD5400. These are MOSFET switches. The Vgs threshold is ~0.1V. It is driven by TTL logic level signals (0,5V). This being the case, if the voltage coming from the current sources goes below -0.1V or above 5V it will not switch correctly. Because the current is so low (450uA), a load of >200Ohms would be required to generate a voltage higher than 0.1V. I assume that the integrator presents as a load lower than this.

When not in uses, both the input and the references switch to a separate path, I’ve not looked at this path in detail. But kind of imagine this is used as a sink, which keeps the current flowing through the references constant…

I’ve been playing with a multislope ADC design. Multislope ADC are often used in high end multimeters, and as I have a mild obsession with 8.5 digit multimeters, I wanted to try making a multislope ADC. The current design, such as it is was developed with significant input from EEVBlog users (see this thread). This post documents initial bring up and tests of the first revision of the PCB. Links to Kicad files, and data used in plots can be found at the end of this post.

Components used in this test

All resistors are standard, cheap 1/4 Watt metal film resistors. The large slopes are 47K. Small slopes 4.7M. The input resistor (R200) is also 47K. The design uses a 2 opamp integrator. Notionally this allows you to combine an opamp with good low frequency response with one with good high frequency response. A voltage divider sits between the two opamps. R9 is 47Ohm, R8 1K. On the output amplifier R3 is 1K and R7 is 470Ohm to give a gain of ~0.5. This allows the Arduino Mega which I’m using to control the amplifier to read almost the full positive range of the integrator output (12V). The integrator capacitor is an NP0 10nF, Murata GRM3195C1E103JA01D. The switches are all DG419s. This includes the part marked DG417 on the schematic, which resets the integrator. All the DG419s are Vishay DG419Bs MSOP8s, except for the integrator which uses an Analog ADG1419BRMZ (I ran out of Vishay DG419s). Update: I attempted to rebuild this circuit using only ADG1419BRMZ, it did not work well. My guess is that there is too much charge injection… charge injection is not listed in the datasheets… I’m using a LTZ1000 reference to supply the slopes. This sits on an 3458A A9 PCB. I’m using a A9 clone from here. All opamps are socketed. In this test I used a NE5534 on the output. An OPA177 and AD711 for the integrator, an AD711 on the input, and an LT1013 to buffer/invert the reference voltage.

Build Issues

There were a few errors in the schematic and layout. These include:

• The banana plug holes are too small for the sockets.
• The output opamp connected incorrectly (power swapped)
• The input opamp was connected incorrectly (I forget the exact issue).
• The reference voltage buffer/inverter was wired incorrectly.
• The reference PCB covers the banana plugs when installed.

These should be resolved in the schematic, but I’ve not fixed the layout yet. In the build you’ll also notice that I’ve hacked around with other parts of the PCB too. This was when I was cutting traces to try and figure out where leakage current was coming from and charging the integration capacitor. In the end this seemed to be coming from flux I couldn’t clean from under the DG419 switches. I removed, cleaned and replaced these, being more conservative with my usage of flux when re-soldering them. This removed most of the leakage current.

Initial tests

When I first brought up the design there was a lot of charge accumulating on the integrator after reset without any of the slopes or the input connected. After about 3 seconds the integrator would rise to the rail voltage (12v). After some investigation, this seemed to be caused by excess flux remaining under the DG419s. After cleaning this out, it takes ~60 seconds for the integrator to charge to the rail voltage. The following plot shows the output as recorded by an Arduino analog input:

I’ve written code to drive the ADC board in a basic dual slope configuration. This works for bother the large and small slopes. In the tests below however I’m using the small slopes only. Arduino code is provided in the notes at the end of this post.

The tests use a DP832 to supply rail voltages (+/- 12 and 5V). A 33220A function generator is used to generate the input (this is probably not particularly low noise/accurate).

The following plot shows a histogram of ADC counts when the input is zero:

And here at 10V:

There’s something weird going on, as in some cases the histogram is bimodal. For example here at 1V:

Integration of positive voltages is also about 3 times quicker than negative voltages. It’s not clear to me why this is. Positive and negative voltages use different reference resistors, however these don’t seem to be significantly different and I need to investigate further.

The positive and negative responses however seem to be quite linear. The following plot shows input voltage versus ADC count. You can see the slope difference between positive and negative voltages quite clearly:

Before moving forward, I’d like to better understand why I’m seeing this difference between positive and negative voltages. I should then be in a position to combine large and small slopes to create a multislope ADC.

Update: I cleaned the board in an ultrasonic cleaner (distiled water, 60 degrees for ~15min, with a small amount of washing up liquid. Then agitated in IPA for ~30min). This seems to have cleared up the slope issue above. Here’s a revised graph:

Notes

PCB Back:

EEV Blog Thread

Data for plots

Kicad files

Hacky code used in this post:

#include <SPI.h>  
  
// name      header   arduino
// SW_RST    2        4
// SW_INPUT2 6        3
// SW_INPUT1 8        2
// SW_REF2B  10       A7
// SW_REF2A  12       A6
// SW_REF1B  14       A5
// SW_REF1A  16       A4
// CMP_OUT   18       A3

#define SW_RST    5
#define SW_INPUT2 3
#define SW_INPUT1 2
#define SW_REF2B  A7
#define SW_REF2A  A6
//#define SW_REF1B  A5 - original
#define SW_REF1B  A1
#define SW_REF1A  A4
//#define CMP_OUT   A3 - original
#define CMP_OUT   A2


void input_off() {
  digitalWrite(SW_INPUT2,HIGH);
  delayMicroseconds(100);
  digitalWrite(SW_INPUT1,LOW);
}

void input_on() {
  digitalWrite(SW_INPUT1,HIGH);
  delayMicroseconds(100);
  digitalWrite(SW_INPUT2,LOW);
}

void references_off() {
  digitalWrite(SW_REF1A,HIGH);
  digitalWrite(SW_REF1B,HIGH);
  digitalWrite(SW_REF2A,HIGH);
  digitalWrite(SW_REF2B,HIGH);
}

int read_cmp() {
  int r = analogRead(CMP_OUT);
  return r;
}

void dump_cmp() {
  int r = read_cmp();
  Serial.print(r);
  Serial.print(" ");
}

void ref_on(int p) {
  digitalWrite(p,LOW);
}

void ref_off(int p) {
  digitalWrite(p,HIGH);
}

void reset_integrator() {
  digitalWrite(SW_RST,HIGH);
  delayMicroseconds(10001);
//  delay(3000);
  digitalWrite(SW_RST,LOW);
}

void setup() {  

  // put your setup code here, to run once:
  Serial.begin(115200);

  pinMode(SW_RST   ,OUTPUT); 
  pinMode(SW_INPUT2,OUTPUT); 
  pinMode(SW_INPUT1,OUTPUT); 
  pinMode(SW_REF2B ,OUTPUT); 
  pinMode(SW_REF2A ,OUTPUT); 
  pinMode(SW_REF1B ,OUTPUT); 
  pinMode(SW_REF1A ,OUTPUT); 
  pinMode(CMP_OUT  ,INPUT ); 
  
  input_off();
  references_off();
  reset_integrator();

 //     ref_on(SW_REF2B); 
  Serial.println("input complete");
  for(;Serial.available() == 0;) {
    dump_cmp();
    Serial.println();
    delay(500);
  }
  Serial.println("running...");
}

void loop() {

  // Serial.println("start");
  input_off();
  delayMicroseconds(1000);
 // Serial.println("inputoff");
  references_off();
 // Serial.println("refoff");
  delayMicroseconds(1000);
  reset_integrator();
 // Serial.println("int reset");
  delayMicroseconds(1000);
  int p = read_cmp();
  int c=0;
  for(;p != 0;) {
    reset_integrator();
    p = read_cmp();
    //Serial.print(p);
    //Serial.print(" ");
    c++;
    if(c>10) break;
  }
  //Serial.println();
  //dump_cmp();

  input_on();
  delayMicroseconds(500);
  input_off();


  int pol = read_cmp();

  // input negative
  if(pol > 0) {
    Serial.print("-");

    unsigned int count=0;
    for(;;) {
      ref_on(SW_REF2B); 
      delayMicroseconds(5);
      ref_off(SW_REF2B);
      int c = read_cmp();
      if(c == 0) break;
      count++;
      if(count > 64000) {Serial.print("B"); count=0;}
    }
    Serial.println(count);
  }

  // input positive
  if(pol >= 0) {
    Serial.print("+");
    unsigned int count=0;
    for(;;) {
      ref_on(SW_REF2A);
      delayMicroseconds(5);
      ref_off(SW_REF2A);
      int c = read_cmp();
      if(c > 0) break;
      count++;
      if(count > 64000) {Serial.print("B"); count=0;}
    }
    Serial.println(count);
  }

}

TDLR; Applying to YC is an interesting experience, and have a clearer process than many VCs. I would recommend it, even for solo founders and science-based startups.

I applied to the YC winter 2019 batch. I viewed the whole process as relatively low probability. YC gets more than 5000 applications. Out to these ~500 get invited to interview onsite.

My idea was for a cheap simple device to read/write DNA. I’ve blogged about my approach before here and here, you can find the complete YC application below. While I wasn’t accepted, I interview with YC a pleasant and worthwhile experience. My hope is that this post will encourage other science based startups and solo founders to apply to YC.

My application was for an idea stage startup. I didn’t spend much time putting the application together, went for a walk to think thing over and then did a couple of takes to create the intro video:

As a solo founder, idea stage, science based startup I thought my chances were quite slim. I fired off the application anyway, as the investment of time on my part was relatively low.

You don’t need a deck, and the focus seems to be on the idea and the team. This is in contrast to most seed stage VCs (even accelerators) who require a deck and likely multiple meetings.

The other difference with YC is the timeline is very clear. Many VCs will keep you hanging, not reply, or ask you to check back in after some vaguely specified goal has been reached. It’s understandable, but can be painful.

YC reply on a fixed timeline [1]. This makes the whole process clearer to everybody involved. After putting in my application, I received an email a few days later requesting a phone screen.

The phone screen was about 10 minutes. Quite high level, and mostly just clarified the play, and how it fits into the DNA sequencing space (see the application below if your interested in further details [1]).

The deadline came and went, and I heard back the day after the official deadline that they’d like me to come to Mountain View to interview.

YC cover your travel expenses up to a limit. Coming from Japan, the travel budget was 1000USD and hotel budget 350USD.

The interview process itself was pretty painless. My interview panel consisted of 3 people. One had a background in Biotech and had in fact worked at a DNA sequencing startup.

The conversation was good, they were very focused. They didn’t focus too hard on the technical aspects of the play. After discussing the play and initial focus, we moved on to talk about how I would beat the current market leader (Illumina).

This wasn’t really the play, Illumina are very cheap on cost per base. But their cost per run is very high (500USD+). The idea was to focus on applications were a very low cost per run (10USD) would be beneficial, bootstraping on DIYBio and Synthetic Biology applications. My thesis is diagnostic instrumentation will likely require a cheap run cost… but throughput isn’t so critical for many applications.

But they wanted to see the Illumina-killer play worked though. This is not unreasonable. While this might not be the pitch, I think it’s reasonable that I should have the idea worked through… I guess that I have the “idea maze” fully explored.

In total the interview lasted about 15 minutes.

I heard back later that evening that I didn’t make it into this batch. They gave detailed feedback (which you’ll find at the end of this post [2]), again this is something you don’t receive with most VCs.

I was left feeling quite positive about YC. The process was very clear, and I think they can do a reasonable job of selecting and funding science heavy startups.

They’re quite unique in a number of aspects. The goal seems to be to create an efficient pipeline for selecting startups that can increase their valuation from a nominal 2MUSD to probably ~20MUSD in a 3 month timeline (and eventually growing to unicorn size).

After the 3 month period is up, you get put in front of a bunch of 2nd stage investors and the hope would be that you raise at this increased valuation.

500 startups are interviewed. From my experience I’d guess they spend <30 minutes evaluating each one. This isn’t enough time to do a deep dive, but it’s probably the point of diminishing returns. After this they have a strong enough signal, to filter 500 startups down to 100 which have a reasonable chance of moving forward.

This pipeline likely works as well for science based startups as traditional tech. And I know that in my batch a DNA sequencing startup was selected, and will be following it with interest.

As for me… I’ll probably put my startup on hold for now. The timing isn’t right for me to move to the US, and working on this idea would likely take more money than I have.

If you’re doing a science based startup in Japan, or I could conceivably help out remotely, please get in touch! (new at sgenomics dot org).

Notes

[1] The interview acceptance came about a day late. Given the volume of applications they have I find this more than acceptable.

[2]

I confirmed with YC that they are happy for me to share the feedback, so here it is!

[3]

Application:

COMPANY

Company name:

Opusone

Company url, if any:

[BLANK]

If you have a demo, what’s the url? For non-software, demo can be a video.

(Please don’t password protect it; just use an obscure url.)

[BLANK]

Describe your company in 50 characters or less.

Read/Write DNA Device

What is your company going to make?

A cheap device to read and write DNA aimed at synthetic biology and DIYBio.

Which category best applies to your company?

Biotech

Is this application in response to a YC RFS?

No

Where do you live now, and where would the company be based after YC?

(List as City A, Country A / City B, Country B.)

Tokyo, Japan

CONTACT

Email address of the founder who is filling out this application:

XXXXXXXXXXXXXXX

Phone number(s):

XXXXXXXXXXX
FOUNDERS

Founders

HACKER NEWS USERNAME NAME EMAIL PROFILE UPDATED
new299 Nava Whiteford XXXXXXXXX yes
Please enter the url of a 1 minute unlisted (not private) YouTube or Youku video introducing the founders. (Follow the Video Guidelines.)

Please tell us about an interesting project, preferably outside of class or work, that two or more of you created together. Include urls if possible.

[BLANK]

How long have the founders known one another and how did you meet? Have any of the founders not met in person?

[BLANK]

PROGRESS

How far along are you?

Idea stage, in process of building proof of concept.

How long have each of you been working on this? Have you been part-time or full-time? Please explain.

1 month.

I started developing the concept about a month ago. I’ve ordered reagents, designed PCBs and sent them out for fabrication.

Which of the following best describes your progress?

Unlaunched

When will you have a prototype or beta?

within 6 months

Do you have revenue?

No

How much money do you spend per month?

1000

How much money does your company have in the bank now?

0

How long is your runway?

(e.g. 5 months)

6 months

If you’ve applied previously with the same idea, how much progress have you made since the last time you applied? Anything change?

[BLANK]

If you have already participated or committed to participate in an incubator, “accelerator” or “pre-accelerator” program, please tell us about it.

[BLANK]

IDEA

Why did you pick this idea to work on? Do you have domain expertise in this area? How do you know people need what you’re making?

I’ve worked at many different (5) DNA sequencing companies at various levels, up to CTO.

I feel like I have a good feel for the pain points in development and have developed a unique angle on sequencing.

I think this is an instrument that every synthetic biology or DIYBio lab needs.

What’s new about what you’re making? What substitutes do people resort to because it doesn’t exist yet (or they don’t know about it)?

Slow turn DNA synthesis or sequencing by an external lab.

Who are your competitors, and who might become competitors? Who do you fear most?

There are large sequencing companies (Illumina) and synthesis companies (Twist).

No-one is targeting something very cheap. Nobody is developing a single device to read and write DNA to my knowledge. An existing synthesis company could potentially pivot into this.

Someone suddenly decide to slash their sequencing costs by 1000 fold. A complete product could come out of the blue which does everything I’m considering, at the same cost, and with loads of money backing it.

What do you understand about your business that other companies in it just don’t get?

They want to grow the existing market. I want to build new ones.

How do or will you make money? How much could you make?

(We realize you can’t know precisely, but give your best estimate.)

I think the global market for DNA synthesis alone could grow to ~20BUSD.

How will you get users? If your idea is the type that faces a chicken-and-egg problem in the sense that it won’t be attractive to users till it has a lot of users (e.g. a marketplace, a dating site, an ad network), how will you overcome that?

I’d like to engage with the DIYBio community, and more traditional hacker spaces, and show what can be done with a read/write DNA instrument.

I would engage in early access projects with synthetic biology labs.

EQUITY

Have you incorporated, or formed any legal entity (like an LLC) yet?

No

If you have not formed the company yet, describe the planned equity ownership breakdown among the founders, employees and any other proposed stockholders.

(This question is as much for you as us.)

Solo founder. I have enough experience to build a proof of concept, but I will need to hire technical leadership. I will need guidance on this. I believe a decent CSO will require cofounder level equity for example (10%+).

Please provide any other relevant information about the structure or formation of the company.

[BLANK]

LEGAL

Are any of the founders covered by noncompetes or intellectual property agreements that overlap with your project? If so, please explain.

[BLANK]

Who writes code, or does other technical work on your product? Was any of it done by a non-founder? Please explain.

I’ve worked on everything so far.

Is there anything else we should know about your company?

(Pending lawsuits, cofounders who have left, etc.)

[BLANK]

OTHERS

If you had any other ideas you considered applying with, please list them. One may be something we’ve been waiting for. Often when we fund people it’s to do something they list here and not in the main application.

* Easy mail order water quality testing.
* Using nanopore for DNA synthesis.
* Offline collaboration tools for use in space.

Please tell us something surprising or amusing that one of you has discovered.

(The answer need not be related to your project.)

[BLANK]

CURIOUS

What convinced you to apply to Y Combinator?

I read hackernews, you seem to treat people fairly and I think would be good people to help me get things off the ground.

How did you hear about Y Combinator?

news.ycombinator.com